As semiconductor devices including integrated circuits (IC) operate at higher frequencies, higher data rates and lower voltages, noise in the power and ground (return) lines and supplying sufficient current to accommodate faster circuit switching becomes an increasingly important problem requiring low impedance in the power distribution system. In order to provide low noise, stable power to the IC, impedance in conventional circuits is reduced by the use of additional surface mount technology (SMT) capacitors interconnected in parallel. The higher operating frequencies (higher IC switching speeds) mean that voltage response times to the IC must be faster. Lower operating voltages require that allowable voltage variations (ripple) and noise become smaller. For example, as a microprocessor IC switches and begins an operation, it calls for power to support the switching circuits. If the response time of the voltage supply is too slow, the microprocessor will experience a voltage drop or power droop that will exceed the allowable ripple voltage and noise margin and the IC will trigger false gates. Additionally, as the IC powers up, a slow response time will result in power overshoot. Power droop and overshoot must be controlled within allowable limits by the use of capacitors that are close enough to the IC that they provide or absorb power within the appropriate response time. This power droop and overshoot are maintained within the allowable limits by the use of capacitors providing or absorbing power in the appropriate response time.
Capacitors for decoupling and dampening power droop or overshoot are generally placed as close to the IC as possible to improve their performance. Conventional designs have capacitors surface mounted on the printed wiring board (PWB) clustered around the IC. In this case, large numbers of capacitors requires complex electrical routing which leads to inductance. As frequencies increase and operating voltages continue to drop, power increases and higher capacitance has to be supplied at increasingly lower inductance levels. A solution would be to incorporate a high capacitance density, thin film ceramic capacitor in the PWB package onto which the IC is mounted. A single layer ceramic capacitor directly under the IC reduces the inductance to as minimum as possible and the high capacitance density provides the capacitance to satisfy the IC requirements. Such a capacitor in the PWB can provide capacitance at a significantly quicker response time and lower inductance.
Embedding ceramic capacitor films in printed wiring boards is known. Capacitors are initially formed on metal foils by depositing a capacitor dielectric material on the foil and annealing it at an elevated temperature. A top electrode is formed on the dielectric to form a fired capacitor on foil structure. The foil is then bonded to an organic laminate structure to create an inner layer panel wherein the capacitor is embedded in the panel. These inner layer panels are then stacked and connected by interconnection circuitry, the stack of panels forming a multilayer printed wiring board.
A high capacitance density capacitor can be achieved by use of a dielectric with a high permittivity or dielectric constant (K) and a thin dielectric. High dielectric constants are well known in ferroelectric ceramics. Ferroelectric dielectric materials with high dielectric constants include perovskites of the general formula ABO3 in which the A site and B site can be occupied by one or more different metals. For example, high K is realized in crystalline barium titanate (BT), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), lead magnesium niobate (PMN) and barium strontium titanate (BST) and these materials are commonly used in surface mount component devices. Barium titanate based compositions are particularly useful as they have high dielectric constants and they are lead free.
Thin film capacitor dielectrics with a thickness of less than 1 micron are well known. Thin films can be deposited on to a substrate by sputtering, laser ablation, chemical vapor deposition, and chemical solution deposition. Initial deposition is either amorphous or crystalline depending upon deposition conditions. Amorphous compositions have low K (approximately 20) and have to be annealed at high temperatures to induce crystallization and produce the desired high K phase. The high K phase in barium titanate based dielectrics can only be achieved when grain sizes exceed 0.1 micron and so annealing temperatures as high as 900° C. may be used.
Chemical solution deposition (CSD) techniques are commonly used to form thin film capacitors on metal foils. CSD techniques are desirable due to their simplicity and low cost. High temperature annealing of barium titanate thin CSD films formed on base metal foils such as copper or nickel, require low oxygen partial pressures to avoid oxidation of the metal. The low oxygen partial pressures, however, often result in high leakage currents under applied bias (current densities) in barium titanate based compositions due to reduction of the dielectric material. In worst case situations, the capacitor may be shorted and dielectric properties cannot be measured. This may be addressed by a subsequent re-oxidation procedure carried out at lower temperatures in which the dielectric and metal foil is exposed to higher partial pressures of oxygen but this results in oxidation of the base metal foil.
A barium titanate CSD composition is disclosed in U.S. National patent application Ser. No. 10/621,796 (U.S. Patent Publication No. 2005-001185). The composition is particularly suitable for forming high capacitance density, ceramic films on copper foil. The precursor composition consists of the following chemicals:
Barium acetate2.6gTitanium isopropoxide2.9mlAcetylacetone2.0mlAcetic acid10.0mlMethanol15ml
However, when annealed at 900° C. in a partial pressure of oxygen of approximately 10−11 atmospheres, the film was conducting and a re-oxidation procedure was necessary to produce parts from which electrical data could be taken. This procedure oxidized the foil and did not necessarily produce optimum capacitor performance, particularly with respect to leakage current density under bias. It is also not cost effective to re-oxidize the dielectric in a separate step. It would be an advantage, therefore, if the barium titanate composition could be doped to produce good electrical performance, particularly a low leakage current density under bias, immediately after the low oxygen partial pressure annealing process.